International company Web Electronic Industry
is taking the candidates in the USA for the position of Local Agent.
We are looking for the trustworthy person with excellent organizational and communicative skills.
Good knowledge of computer and business relations practice will be your advantage.
This is a part-time job which can be combined with any permanent or another part-time job.
Average workload is up to 8 hours a week.
No special experience is necessary. Excellent compensation
package, the salary starts from $20,000 a year.
If you got interested in our vacancy and you have any questions,
please contact us staff(*)w-ei.com
The offer is for USA citizens only.
Yet, there remains a problem with the "nano" in both nanoscience and nanotechnology. "Nanotechnology's a term with not too much new in it. It existed a long time ago," says Dai. Indeed, the characteristic length of bonds that have always been under scrutiny in the molecular sciences is on the order of a nanometer. Chidsey adds, "I worry that the term confuses people about what's important: the length scale itself is not important." Rather, it is the novel properties that structures exhibit at the nanoscale that is. As Dai puts it, "We work on carbon nanotubes not because they are small, but because they are interesting. They just happen to be nano." For all the problems with the term nanotechnology, though, it may have done some good. Chidsey remarks, "Just as nanotechnology has attracted the attention of outsiders, it also stimulates us internally: it provides a context for tackling and defining grand challenges-things so out there you wouldn't tackle them otherwise." A decade ago, Saraswat's research group was the first to begin developing a new kind of chip architecture: the 3-dimensional integrated circuit (3-D IC). Compared to the 2-D planar chips in computers today, 3-D chips can provide the same processing power with a reduced chip surface area. Also, instead of having long, twisting highways of wires, the stacked chips in 3-D ICs allow for short wires much like elevator shafts, as Professor Chidsey puts it-mitigating the problem of delay in the wires. Moreover, 3-D IC architecture allows the integration of all kinds of chips, since chips that require different technologies or materials can be stacked together. The main challenge in 3-D IC design is performance-weakening heat dissipation, which is already a problem in 2-D chips, as any Stanford students who have written a term paper with their laptops on their laps know. The multi-layer design of 3-D ICs exacerbates the problem, and Mechanical Engineering Professors Ken Goodson and Tom Kenney have been working on flowing fluid through microchannels incorporated in the chips to conduct the heat away. Received on Sat Sep 15 2007 - 23:12:07 EDT
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